This invention relates to a decoder, which is suitably designed to operate with a low supply voltage, and to a semiconductor memory using such a decoder.
At present, main-frame computers typically have their high-speed cache memory and control memory formed of a bipolar memory or BiCMOS memory. The bipolar memory and BiCMOS memory have a property of very fast operation, although their power consumption is large to some extent. Due to the recent trend of down-sizing of IC memory devices, their element transistors have a lower breakdown voltage, and therefore it becomes necessary to design such bipolar memories and BiCMOS memories to operate with low supply voltages.
An example of the conventional decoder intended for the high-speed operation of a bipolar memory or BiCMOS memory is described in an article entitled "Fabrication of a large-capacity, high-speed SRAM based on the BiCMOS technology" (in The transactions C of The Institute of Electronics, Information and Communication Engineers of Japan, Vol. J70-C, No.6, pp.783-790, published in June 1987).
This decoder uses series-gate circuits to reduce the number of gates thereby to speed up the operation. However, the use of series-gate circuits makes difficult the circuit design for low supply voltage operation.
FIG. 3 shows a decoder developed by the inventors from conventional decoders during their studies leading to the present invention. The arrangement of FIG. 3 is suitable for a high-speed bipolar memory and BiCMOS memory. The circuit consists of input buffers IB1 and IB2 and a decoder DEC. The following Table 1 is a truth table between the inputs IN1 and IN2 and the outputs OUT1 through OUT4 of the circuit.
TABLE 1 ______________________________________ IN1 IN2 OUT1 OUT2 OUT3 OUT4 ______________________________________ L L L H H H H L H L H H L H H H L H H H H H H L ______________________________________
The decoder shown in FIG. 3 has one of the outputs OUT1 through OUT4 becoming a low (L) level in response to a certain combination of the inputs IN1 and IN2, and this kind of decoder will be called "L decoder".
The study of this decoder by the inventors of the present invention revealed that the bipolar transistors Q1 (or Q2) and Q3 in serial connection forms a series-gate circuit, making the circuit design for low supply voltage operation difficult as will be explained in the following discussion.
For the output signal of the decoder having a voltage swing of V.sub.OUT volts, the transistor Q1 has a high collector voltage level H of 0 volt and a low voltage level L of -V.sub.OUT volts. Generally, a bipolar transistor operating in saturation mode has its operating speed reduced. Therefore in order for the decoder to operate fast, the transistor Q1 must operate in the non-saturation mode. For the non-saturant operation of the Q1, it must have a base voltage that is always lower than the collector voltage, i.e., always lower than -V.sub.OUT. Accordingly, the transistor Q1 must have an emitter voltage lower than -V.sub.OUT -V.sub.BE (where V.sub.BE is a base-to-emitter voltage of a bipolar transistor).
For the high-speed operation of the whole gate circuit, the transistor Q3 must operate in the non-saturation mode. For the non-saturant operation of the Q3, it must have a base voltage that is always lower than -V.sub.OUT -V.sub.BE. Accordingly, the transistor Q3 must have an emitter voltage lower than -V.sub.OUT -2.times.V.sub.BE. With a current source I1 having an operating voltage of V1, the emitter supply voltage V.sub.EE must be lower than -V.sub.OUT -2.times.V.sub.BE -V1. In other words, the supply voltage in terms of the absolute value .vertline.V.sub.EE .vertline. cannot be smaller than V.sub.OUT +2.times.V.sub.BE +V1. On this account, a bipolar memory or BiCMOS memory using this decoder cannot have a supply voltage lower than V.sub.OUT +2.times.V.sub.BE +V1.